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etc5064/64-x etc5067/67-x september 2003 power amplifier serial interface codec/filter with receive ? ordering numbers: etc5064fn etc5064fn-x etc5067fn etc5067fn-x . complete codec and filtering sys- tem including : - transmit high-pass and low-pass filtering. - receive low-pass filter with sin x/x correction. - active rc noise filter. - m -law or a-law compatible coder and de- coder. - internal precision voltage reference. - serial i/o interface. - internal auto-zero circuitry. - receive push-pull power amplifiers. . m -law etc5064 . a-law etc5067 . meets or exceeds all d3/d4 and ccitt specifications. . 5 v operation. . low operating power-typically 70 mw . power-down standby mode-typically 3 mw . automatic power down . ttl or cmos compatible digital inter- faces . maximizes line interface card cir- cuit density . 0 c to 70 c operation: etc5064/67 . C40 c to 85 c operation: etc5064-x/67-x description the etc5064 ( m -law), etc5067 (a-law) are mono- lithic pcm codec/filters utilizing the a/d and d/a conversion architecture shown in the block dia- grams and a serial pcm interface. the devices are fabricated using double-poly cmos process. similar to the etc505x family, these devices fea- ture an additional receive power amplifier to pro- vide push-pull balanced output drive capability. the receive gain can be adjusted by means of two ex- ternal resistors for an output level of up to 6.6 v across a balanced 600 w load. also included is an analog loopback switch and ts x output. dip20 (plastic) n plcc20 fn so20 d ordering numbers: etc5064n etc5064n-x etc5067n etc5067n-x ordering numbers: etc5064d etc5064d-x etc5067d etc5067d-x 1/18
block diagram (etc5064 - etc5064-x - etc5067 - etc5067-x) pin connections (top views) dip20 & so20 plcc20 etc5064 - etc5064-x - etc5067 - etc5067-x 2/18
pin description name pin type (*) n description vpo + o 1 the non-inverting output of the receive power amplifier gnda gnd 2 analog ground. all signals are referenced to this pin. vpo - o 3 the inverting output of the receive power amplifier vpi i 4 inverting input to the receive power amplifier. also powers down both amplifiers when connected to v bb . vf r o o 5 analog output of the receive filter. v cc s6 positive power supply pin. v cc = +5v 5% fs r i 7 receive frame sync pulse which enable bclk r to shift pcm data into d r . fs r is an 8khz pulse train. see figures 1 and 2 for timing details. d r i 8 receive data input. pcm data is shifted into d r following the fs r leading edge bclk r /clksel i 9 the bit clock which shifts data into d r after the fs r leading edge. may vary from 64khz to 2.048mhz. alternatively, may be a logic input which selects either 1.536mhz/1.544mhz or 2.048mhz for master clock in synchronous mode and bclk x is used for both transmit and receive directions (see table 1). this input has an internal pull-up. mckl r /pdn i 10 receive master clock. must be 1.536mhz, 1.544mhz or 2.048mhz. may be asynchronous with mclk x , but should be synchronous with mclk x for best performance. when mclk r is connected continuously low, mclk x is selected for all internal timing. when mclk r is connected continuously high, the device is powered down. mclk x i 11 transmit master clock. must be 1.536mhz, 1.544mhz or 2.048mhz. may be asynchronous with mclk r . bclk x i 12 the bit clock which shifts out the pcm data on d x . may vary from 64khz to 2.048mhz, but must be synchronous with mclk x . d x o13 the tri-state a pcm data output which is enabled by fs x . fs x i 14 transmit frame sync pulse input which enables bclk x to shift out the pcm data on d x . fs x is an 8khz pulse train. see figures 1 and 2 for timing details. ts x o 15 open drain output which pulses low during the encoder time slot. must to be grounded if not used. anlb i 16 analog loopback control input. must be set to logic 0 for normal operation. when pulled to logic 1, the transmit filter input is disconnected from the output of the transmit preamplifier and connected to the vpo + output of the receive power amplifier. gs x o 17 analog output of the transmit input amplifier. used to set gain externally. vf x i - i 18 inverting input of the transmit input amplifier. vf x i + i 19 non-inverting input of the transmit input amplifier. v bb s20 negative power supply pin. v bb = -5v 5% (*) i: input, o: output, s: power supply. tri-state is a trademark of national semiconductor corp. etc5064 - etc5064-x - etc5067 - etc5067-x 3/18
functional description power-up when power is first applied, power-on reset circuitry initializes the device and places it into the power- down mode. all non-essential circuits are deacti- vated and the d x and vf r o outputs are put in high impedance states. to power-up the device, a logical low level or clock must be applied to the mclk r /pdn pin and fs x and/or fs r pulses must be present. thus 2 power-down control modes are available. the first is to pull the mclk r /pdn pin high; the alternative is to hold both fs x and fs r in- puts continuously low. the device will power-down approximately 2 ms after the last fs x pulse. the tri-state pcm data output, d x , will remain in the high impedance state until the second fs x pulse. synchronous operation for synchronous operation, the same master clock and bit clock should be used for both the transmit and receive directions. in this mode, a clock must be applied to mclk x and the mclk r /pdn pin can be used as a power-down control. a low level on mclk r /pdn powers up the device and a high level powers down the device. in either case, mclkx will be selected as the master clock for both the transmit and receive circuits. a bit clock must also be applied to bclk x and the bcl r /clksel can be used to se- lect the proper internal divider for a master clock of 1.536 mhz, 1.544 mhz or 2.048 mhz. for 1.544 mhz operation, the device automatically compen- sates for the 193 rd clock pulse each frame. with a fixed level on the bclk r /cksel pin, bclk x will be selected as the bit clock for both the transmit and receive directions. table 1 indicates the fre- quencies of operation which can be selected, de- pending on the state of bclk r /clksel. in this syn- chronous mode, the bit clock, bclk x , may be from 64 khz to 2.048 mhz, but must be synchronous with mclk x . each fs x pulse begins the encoding cycle and the pcm data from the previous encode cycle is shift out of the enabled d x output on the positive edge of bclk x . after 8 bit clock periods, the tristate d x output is returned to a high impedance state. with an fs r pulse, pcm data is latched via the d r input on the negative edge of bclk x (or on bckl r if running). fs x and fs r must be synchronous with mclkx/ r . asynchronous operation for asynchronous operation, separate transmit and receive clocks may be applied. mclk x and mclk r must be 2.048 mhz for the etc5067 or 1.536 mhz, 1.544 mhz for the etc5064, and need not be syn- chronous. for best transmission performance, how- ever, mclk r should be synchronous with mclk x , which is easily achieved by applying only static logic levels to the mclk r /pdn pin. this will automatically connect mclk x to all internal mclk r functions (see pin description). for 1.544 mhz operation, the de- vice automatically compensates for the 193rd clock pulse each frame. fs x starts each encoding cycle and must be synchronous with mclk x and bclk x . fs r starts each decoding cycle and must be syn- chronous with bclk r . bclk r must be a clock, the logic levels shown in table 1 are not valid in asyn- chronous mode. bclk x and bclk r may operate from 64khz to 2.048 mhz. short frame sync operation the device can utilize either a short frame sync pulse or a long frame sync pulse. upon power initiali- zation, the device assumes a short frame mode. in this mode, both frame sync pulses. fs x and fs r , must be one bit clock period long, with timing rela- tionships specified in figure 2. with fs x high during a falling edge of bclk r , the next rising edge of bclk x enables the d x tri-state output buffer, which will output the sign bit. the following seven ris- ing edges clock out the remaining seven bits, and the next falling edge disables the d x output. with fs r high during a falling edge of bclk r (bclk x in synchronous mode), the next falling edge of bclk r latches in the sign bit. the following seven falling edges latch in the seven remaining bits. both de- vices may utilize the short frame sync pulse in syn- chronous or asynchronous operating mode. long frame sync operation to use the long frame mode, both the frame sync pulses, fs x and fs r , must be three or more bit clock periods long, with timing relationships specified in figure 3. based on the transmit frame sync fs x , the device will sense whether short or long frame sync table 1: selection of master clock frequencies. bclkr/clksel master clock frequency selected etc5067 etc5067-x etc5064 etc5064-x clocked 2.048mhz 1.536mhz or 1.544mhz 0 1.536mhz or 1.544mhz 2.048mhz 1 (or open circuit) 2.048mhz 1.536mhz or 1.544mhz etc5064 - etc5064-x - etc5067 - etc5067-x 4/18
pulses are being used. for 64 khz operation, the frame sync pulses must be kept low for a minimum of 160 ns (see fig 1). the d x tri-state output buffer is enabled with the rising edge of fs x or the rising edge of bclk x , whichever comes later, and the first bit clocked out is the sign bit. the following seven bclk x rising edges clock out the remaining seven bits. the d x output is disabled by the falling bclk x edge following the eighth rising edge, or by fs x going low, whichever comes later. a rising edge on the receive frame sync pulse, fs r , will cause the pcm data at d r to be latched in on the next eight falling edges of bclk r (bclk x in synchronous mode). both devices may utilize the long frame sync pulse in synchronous or asynchronous mode. transmit section the transmit section input is an operational amplifier with provision for gain adjustment using two external resistors, see figure 4. the low noise and wide band- width allow gains in excess of 20 db across the audio passband to be realized. the op amp drives a unity gain filter consisting of rc active pre-filter, followed by an eighth order switched-capacitor bandpass filter directly drives the encoder sample- and-hold circuit. the a/d is of companding type ac- cording to a-law (etc5067 and etc5067-x) or m - law (etc5064 and etc5064-x) coding conven- tions. a precision voltage reference is trimmed in manufacturing to provide an input over load (t max ) of nominally 2.5v peak (see table of transmission characteristics). the fs x frame sync pulse controls the sampling of the filer output, and then the succes- sive-approximation encoding cycle begins. the 8-bit code is then loaded into a buffer and shifted out through d x at the next fs x pulse. the total encoding delay will be approximately 165 m s (due to the trans- mit filter) plus 125 m s (due to encoding delay), which totals 290 m s. any offset voltage due to the filters or comparator is cancelled by sign bit integration. receive section the receive section consist of an expanding dac which drives a fifth order switched-capacitor low pass filter clocked at 256khz. the decoder is a-law (etc5067 and etc5067-x) or m Claw (etc5064 and etc5064-x) and the 5 th order low pass filter corrects for the sin x/x attenuation due to the 8khz sample and hold. the filter is then followed by a 2 nd order rc active post-filter and power amplifier capable of driving a 600 w load to a level of 7.2dbm. the receive section is unity-gain. upon the oc- curence of fs r , the data at the d r input is clocked in on the falling edge of the next eight bclk r (bckl x ) periods. at the end of the decoder time slot, the decoding cycle begins, and 10 m s later the de- coder dac output is updated. the total decoder de- lay is about10 m s (decoder up-date) plus 110 m s (fil- ter delay) plus 62.5 m s (1/2 frame), which gives ap- proximately 180 m s. receive power amplifiers two inverting mode power amplifiers are provided for directly driving a matched line interface trans- former. the gain of the first power amplifier can be adjusted to boost the 2.5v peak output signal from the receive filter up 3.3v peak into an unbalanced 300 w load, or 4.0v into an unbalanced 15k w load. the second power amplifier is internally connected in unity-gain inverting mode to give 6db of signal gain for balanced loads. maximum power transfer to a 600 w subscriber line termination is obtained by differientially driving a balanced transformer with a ? ` ` 2 : 1 turns ratio, as shown in figure 4. a total peak power of 15.6dbm can be delivered to the load plus termination. both power amplifier can be powered down independently from the pdn input by connect- ing the vpi input to v bb saving approximately 12 mw of power. absolute maximum ratings symbol parameter value unit v cc v cc to gnda 7 v v bb v bb to gnda -7 v v in , v out voltage at any analog input or output v cc +0.3 to v bb -0.3 v voltage at any digital input or output v cc +0.3 to gnda -0.3 v t oper operating temperature range: etc5064/67 etc5064-x/67-x -25 to +125 -40 to +125 c c t stg storage temperature range -65 to +150 c lead temperature (soldering, 10 seconds) 300 c etc5064 - etc5064-x - etc5067 - etc5067-x 5/18
electrical operating characteristics v cc = 5.0v 5%, v bb = -5v 5%, gnda = 0v, t a = 0 c to 70 c (etc5064-x/67-x: t a = C40 c to 85 ), unless otherwise noted; typical characteristics specified at v cc = 5.0v, v bb =-5.0v, t a = 25 c; all signals are refer- enced to gnda. digital interface (all devices) symbol parameter min. typ. max. unit v il input low voltage 0.6 v v ih input high voltage 2.2 v v ol output low voltage i l = 3.2 ma d x i l = 3.2 ma, open drain ts x 0.4 0.4 v v v oh output high voltage ih = 3.2 ma d x 2.4 v i il input low current (gnda v in v il )all digital inputs except bclk r C 10 10 m a i ih input high current (v ih v in v cc ) except anlb C 10 10 m a analog interface with transmit input amplifier (all devices) symbol parameter min. typ. max. unit i i xa input leakage current vfxi + or vfxi C (C 2.5 v v + 2.5 v) C 200 200 na r i xa input resistance vf x i + or vf x i C (C 2.5 v v + 2.5 v) 10 m w r o xa output resistance (closed loop, unity gain) 1 3 w r l xa load resistance gs x 10 k w c l xa load capacitance gs x 50 pf v o xa output dynamic range (r l 3 10 k w ) gs x C 2.8 +2.8 v a v xa voltage gain (vf x i + to gs x ) 5000 v/v f u xa unity gain bandwidth 1 2 mhz v os xa offset voltage C 20 20 mv v cm xa common-mode voltage C 2.5 2.5 v cmrrxa common-mode rejection ratio 60 db psrrxa power supply rejection ratio 60 db analog interface with receive filter (all devices) symbol parameter min. typ. max. unit r o rf output resistance vf r o13 w r l rf load resistance (vf r o = 2.5 v) 10 k w c l rf load capacitance 25 pf vos r o output dc offset voltage C 200 200 mv etc5064 - etc5064-x - etc5067 - etc5067-x 6/18
analog interface with power amplifiers (all devices) symbol parameter min. typ. max. unit ipi input leakage current (C 1.0 v vpi 1.0 v) C 100 100 na ripi input resistance (C 1.0 vpi 1.0 v) 10 m w vios input offset voltage C 25 25 mv rop output resistance (inverting unityCgain at vpo + or vpo C )1 w f c unityCgain bandwidth, open loop (vpo C ) 400 khz c l p load capacitance (vpo + or vpo C to gnda) r l 3 1500 w r l = 600 w r l = 300 w 100 500 1000 pf gap + gain vpo C to vpo + to gnda, level at vpo C = 1. 77 vrms (+ 3 dbmo) C 1 v/v psrrp power supply rejection of v cc or v bb (vpo C connected to vpi) 0 khz C 4 khz 0 khz C 50 khz 60 36 db power dissipation (all devices) symbol parameter min. typ. max. unit i cc 0 power-down current at etc6064/67 etc5064-x/67-x 0.5 0.5 1.5 ma ma i bb 0 power-down current at etc6064/67 etc5064-x/67-x 0.05 0.05 0.3 0.4 ma ma i cc 1 active current at etc6064/67 etc5064-x/67-x 7.0 7.0 10.0 12.0 ma ma i bb 1 active current at etc6064/67 etc5064-x/67-x 7.0 7.0 10.0 12.0 ma ma electrical operating characteristics (continued) etc5064 - etc5064-x - etc5067 - etc5067-x 7/18
all timing specifications symbol parameter min. typ. max. unit 1/t pm frequency of master clocks mclk x and mclk r depends on the device used and the bclk r /clksel pin 1.536 2.048 1.544 mhz t wmh width of master clock high mclk x and mclk r 160 ns t wml width of master clock low mclk x and mclk r 160 ns t rm rise time of master clock mclk x and mclk r 50 ns t fm fall time of master clock mclk x and mclk r 50 ns t pb period of bit clock 485 488 15.725 ns t wbh width of bit clock high (v ih = 2.2 v) 160 ns t wbl width of bit clock low (v il = 0.6 v) 160 ns t rb rise time of bit clock (t pb = 488 ns) 50 ns t fb fall time of bit clock (t pb = 488 ns) 50 ns t sbfm set-up time from bclk x high to mclk x falling edge. (first bit clock after the leading edge of fs x ) 100 ns t hbf holding time from bit clock low to the frame sync (long frame only) 0ns t sfb set-up time from frame sync to bit clock (long frame only) 80 ns t hbfi hold time from 3rd period of bit clock fs x or fs r low to frame sync (long frame only) 100 ns t dzf delay time to valid data from fs x or bclk x , whichever comes later and delay time from fsx to data output disabled (c l = 0 pf to 150 pf) 20 165 ns t dbd delay time from bclk x high to data valid (load = 150 pf plus 2 lsttl loads) 0 150 ns t dzc delay time from bclk x low to data output disabled 50 165 ns t sdb set-up time from d r valid to bclk r/x low 50 ns t hbd hold time from bclk r/x low to d r invalid 50 ns t hold holding time from bit clock high to frame sync (short frame only) 0 ns t sf set-up time from fs x/r to bclk x/r low (short frame sync pulse) - note 1 80 ns t hf hold time from bclk x/r low to fs x/r low (short frame sync pulse) - note 1 100 ns t xdp delay time to ts x low (load = 150 pf plus 2 lstti loads) 140 ns t wfl minimum width of the frame sync pulse (low level) (64 bit/s operating mode) 160 ns note : 1.for short frame sync timing. fs x and fs r must go high while their respective bit clocks are high. figure 1 : 64 k bits/s timing diagram. (see next page for complete timing) etc5064 - etc5064-x - etc5067 - etc5067-x 8/18
figure 2 : short frame sync timing. etc5064 - etc5064-x - etc5067 - etc5067-x 9/18
figure 3 : long frame sync timing. etc5064 - etc5064-x - etc5067 - etc5067-x 10/18
transmission characteristics (all devices) t a = 0c to 70c (etc5064-x/67-x: t a = C40 c to 85 ), v cc = 5v 5%, v bb = C 5v 5%, gnda = 0v, f = 1.02khz, v in = 0dbm0 transmit input amplifier connected for unityCgain nonCinverting. (unless otherwise specified). amplitude response symbol parameter min. typ. max. unit absolute levels - nominal 0 dbm0 is 4 dbm (600 w ). 0 dbm0 1.2276 vrms t max max overload level 3.14 dbm0 etc5067 3.17 dbm0 etc5064 2.492 2.501 vpk g xa transmit gain, absolute (t a = 25 c, v cc = 5v, v bb = -5v) input at gs x = 0dbm0 at 1020hz -0.15 0.15 db gxr transmit gain, relative to gxa f = 16hz f = 50hz f = 60hz f = 180hz f = 200hz f = 300hz -3000hz f = 3200hz (etc5064-x/67-x) f = 3300hz f = 3400hz f = 4000hz f = 4600hz and up, measure response from ohz to 4000hz - - - -2.8 -1.8 -0.15 -0.35 -0.35 -0.7 -40 -30 -26 -0.2 -0.1 0.15 0.20 0.05 0 -14 -32 db g xat absolute transmit gain variation with temperature t a = 0 c to +70 c t a = C40 c to +85 c (etc5064-x/67-x) -0.1 -0.15 0.1 0.15 db g xav absolute transmit gain variation with supply voltage (v cc = 5v 5%, v bb = -5v 5%) -0.05 0.05 db g xrl transmit gain variation with level sinusolidal test method reference level = -10dbm0 vf x i + = -40dbm0 to +3dbm0 vf x i + = -50dbm0 to -40dbm0 vf x i + = -55dbm0 to -50dbm0 -0.2 -0.4 -1.2 0.2 0.4 1.2 db g ra receive gain, absolute (t a = 25 c, v cc = 5v, v bb = -5v) input = digital code sequence for 0dbm0 signal at 1020hz -0.15 0.15 db g rr receive gain, relative to g ra f = 0hz to 3000hz f = 3200hz (etc5064-x/67-x) f = 3300hz f = 3400hz f = 4000hz -0.15 -0.35 -0.35 -0.7 0.15 0.20 0.05 0 -14 db g rat absolute receive gain variation with temeperature t a = 0 c to +70 c t a = C40 c to +85 c (etc5064-x/67-x) -0.1 -0.15 0.1 0.15 db g rav absolute receive gain variation with supply voltage (v cc = 5v 5%, v bb = -5v 5%) -0.05 0.05 db g rrl receive gain variation with level sinusoidal test method; reference input pcm code corresponds to an ideally encoded -10dbm0 signal pcm level = -40dbm0 to +3dbm0 pcm level = -50dbm0 to -40dbm0 pcm level = -55dbm0 to -50dbm0 -0.2 -0.4 -1.2 0.2 0.4 1.2 db v ro receive filter output at vf r o r l = 10k w -2.5 2.5 v etc5064 - etc5064-x - etc5067 - etc5067-x 11/18
transmission characteristics (continued) . envelope delay distortion with frequency symbol parameter min. typ. max. unit d xa transmit delay, absolute (f = 1600 hz) 290 315 m s d xr transmit delay, relative to d xa f = 500 hz-600 hz f = 600 hz-800 hz f = 800 hz-1000 hz f = 1000 hz-1600 hz f = 1600 hz-2600hz f = 2600 hz-2800 hz f = 2800 hz-3000 hz 195 120 50 20 55 80 130 220 145 75 40 75 105 155 m s d ra receive delay, absolute (f = 1600 hz) 180 200 m s d rr receive delay, relative to d ra f = 500 hz-1000 hz f = 1000 hz-1600 hz f = 1600 hz-2600 hz f = 2600 hz-2800 hz f = 2800 hz-3000 hz C 40 C 30 C 25 C 20 70 100 145 90 125 175 m s noise symbol parameter min. typ. max. unit n xp transmit noise, p message (a-law, vf x i + = 0 v) weighted 1) etc5064 etc5064-x C 74 C 74 C 69 C 67 dbm0p dbm0p n rp receive noise, p message weighted (a-law, pcm code equals positive zero) C 82 C 79 dbm0p n xc transmit noise, c message weighted ( m -law, vfxi + = 0 v) etc5064 etc5064-x 12 12 15 16 dbrnc0 dbrnc0 n rc receive noise, c message weighted ( m -law, pcm code equals alternating positive and negative zero) 8 11 dbrnc0 n rs noise, single frequency f = 0 khz to 100 khz, loop around measurement, vf x i + = 0 v C 53 dbm0 ppsr x positive power supply rejection, transmit (note 2) v cc = 5.0 v dc + 100 mvrms, f = 0 khz-50 khz 40 dbp npsr x negative power supply rejection, transmit (note 2) v bb = 5.0 v dc + 100 mvrms, f = 0 khz-50 khz 40 dbp ppsr r positive power supply rejection, receive (pcm code equals positive zero, v cc = 5.0 v dc + 100 mvrms) f = 0 hz-4000hz a law m law f = 4 khz-25 khz f = 25 khz-50 khz 40 40 40 36 dbp dbc db db npsr r negative power supply rejection, receive (pcm code equals positive zero, v bb = C 5.0 v dc + 100 mvrms) f = 0 hz-4000hz a law m law f = 4 khz-25 khz f = 25 khz-50 khz 40 40 40 36 dbp dbc db db sos spurious out-of-band signals at the channel output 0 dbm0, 300 hz-3400 hz input pcm applied at d r 4600 hz-7600 hz 7600 hz-8400 hz 8400 hz-100,000 hz C32 C40 C32 db db db etc5064 - etc5064-x - etc5067 - etc5067-x 12/18
transmission characteristics (continued) . distortion symbol parameter min. typ. max. unit std x or std r signal to total distortion (sinusoidal test method) transmit or receive half-channel level = 3.0 dbm0 = 0 dbm0 to C 30 dbm0 = C 40 dbm0 xmt rcv = C 55 dbm0 xmt rcv 33 36 29 30 14 15 dbp (alaw) dbc ( m law) sfd x single frequency distortion, transmit (t a = 25 c) C 46 db sfd r single frequency distortion, receive (t a = 25 c) C 46 db imd intermodulation distortion loop around measurement, vf x i + = C 4 dbm0 to C 21 dbm0, two frequencies in the range 300 hz-3400 hz C 41 db crosstalk symbol parameter min. typ. max. unit ct x-r transmit to receive crosstalk, 0dbm0 transmit f = 300 hz-3400 hz, d r = steady pcm code etc5064/67 etc5064-x/67-x C 90 C 75 C 65 db db ct r-x receive to transmit crosstalk, 0dbm0 receive level (note 2) f = 300 hz-3400 hz, vf x i = 0 v etc5064/67 etc5064-x/67-x C 90 C 70 C 65 db db power amplifiers symbol parameter min. typ. max. unit v ol maximum 0 dbm0 level for better than 0.1 db linearity over the range 10 dbm0 to + 3 dbm0 (balanced load, r l connected between vpo + and vpo C ) r l = 600 w r l = 1200 w r l = 30 k w 33 3.5 4.0 vrms s/d p signal/distortion r l = 600 w , 0 dbm0 50 db notes : 1. measured by extrapolation from the distortion test results. 2. ppsrx, npsrx, ctrCx measured with a C50dbm0 activating signal applied at vf x i + encoding format at d x output a-law (including even bit inversion) m law v in (at gs x ) = + full-scale 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 v in (at gs x ) = 0 v 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 v in (at gs x ) = C full-scale 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 etc5064 - etc5064-x - etc5067 - etc5067-x 13/18
application information power supplies while the pins at the etc506x family are well pro- tected against electrical misure, it is recommended that the standard cmos practice be followed, en- suring that ground is connected to the device before any other connections are made. in applications where the printed circuit board may be plugged into a "hot" socket with power and clocks already pre- sent, an extra long ground pin in the connector should be used. all ground connections to each device should meet at a common point as close as possible to the gnda pin. this minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1 m f supply decoupling capacitors should be con- nected from this common ground point to vcc and vbb as close to the device as possible. for best performance, the ground point of each codec/filter on a card should be connected to a common card ground in star formation, rather than via a ground bus. this common ground point should be decoupled to vcc and vbb with 10 m f capaci- tors. figure 4 : typical asynchronous application. etc5064 - etc5064-x - etc5067 - etc5067-x 14/18
11 0 11 20 a e b d e l k h a1 c so20mec h x 45? so20 dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.1 0.3 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.6 13 0.496 0.512 e 7.4 7.6 0.291 0.299 e 1.27 0.050 h 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.4 1.27 0.016 0.050 k 0? (min.)8? (max.) outline and mechanical data etc5064 - etc5064-x - etc5067 - etc5067-x 15/18
3 2 1 20 19 4 5 6 7 8 9 10111213 m1 m1 b a 14 15 16 17 18 g (seating plane coplanarity) plcc20me e e f d2 d1 d m m plcc20 dim. mm inch min. typ. max. min. typ. max. a 9.78 10.03 0.385 0.395 b 8.89 9.04 0.350 0.356 d 4.2 4.57 0.165 0.180 d1 2.54 0.100 d2 0.56 0.022 e 7.37 8.38 0.290 0.330 e 1.27 0.050 f 0.38 0.015 g 0.101 0.004 m 1.27 0.050 m1 1.14 0.045 outline and mechanical data etc5064 - etc5064-x - etc5067 - etc5067-x 16/18
dip20 dim. mm inch min. typ. max. min. typ. max. a1 0.254 0.010 b 1.39 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 d 25.4 1.000 e 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 f 7.1 0.280 i 3.93 0.155 l 3.3 0.130 z 1.34 0.053 outline and mechanical data etc5064 - etc5064-x - etc5067 - etc5067-x 17/18
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the conse- quences of use of such information nor for any infringement of patents or other rights of third parties which may result from i ts use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentione d in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmi- croelectronics products are not authorized for use as critical components in life support devices or systems without express wr itten approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia C belgium - brazil - canada - china C czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com etc5064 - etc5064-x - etc5067 - etc5067-x 18/18

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